Altera

WELCOME TO OUR SEMINARS

Overview

Founded in 2000, the Laboratory of Digital Technologies of the Department of Design of Electronic Digital Equipment (DEDEC) of the Faculty of Electronics of the National Technical University of Ukraine (NTUU) “Kyiv Polytechnic Institute” (“KPI”) is a well-established competence center specializing in programmable logic and digital signal processing (DSP). Focus areas are design, training and consultancy.

With market expertise in aerospace, wire line communications, computing, industrial, medical, military, test and measurement, and industrial control systems for different objects, display control, motor control, CAN, SPDIF, and I2C, the Laboratory of Digital Technologies of NTUU “KPI” is ready to provide the training you need to successfully design with Altera® products.

Technology expertise includes:

High-speed interfaces
Design of high-speed serial interfaces, board layout, and signal integrity analysis
Buses and interfaces
PCI, PCI Express
Scientific-engineering applications
DSP (different cores), video and image processing

Instructor-Led Training

The Laboratory of Digital Technologies of NTUU “KPI” offers the following instructor-led courses in the Ukraine.

Course Title Description
The Quartus II Software Design Series:
Foundation Learn the basics of Quartus® II design software, including pin planner, device I/O assignments, clock and I/O constraints assignment , and analysis of clock and I/O timing to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, compile & analyze the results using TimeQuest, the timing analyzer in the Quartus II software.
The Quartus II Software Design Series:
Timing Analysis Learn advanced features of the Quartus II design software that will enable you to constrain and analyze a design for timing using the TimeQuest timing analyzer.
The Quartus II Software Design Series:
Verification Explore the advanced features of Quartus II software, including SignalTap® II, ModelSim®, incremental design changes, in-system memory content editor, and embedded logic analyzer that will enable you to verify your FPGA design.
The Quartus II Software Design Series:
Optimization Learn how to shorten your design cycle as well as improve your design performance and utilization using the LogicLock™ regions, incremental compilation, top-down and bottom-up design flows, HDL coding styles, design space explorer, and power consumption reduction features of Quartus II software.
Introduction to VHDL Learn the VHDL high level hardware description and design language, and its use in programmable logic design.
Designing with the Nios II Processor
and SOPC Builder Learn how to integrate design in a Nios® II 32-bit microprocessor and implement it as an embedded soft processor complete with HAL API functions in an Altera FPGA.. Then, integrate the Nios II 32-bit microprocessor and test it in an Altera FPGA. Learn how to configure and compile designs using Quartus II software and the SOPC Builder tool as well as how to develop and run embedded software in the Nios II Integrated Development Environment (IDE).
Contact Information

National Technical University of Ukraine
”Kyiv Polytechnic Institute”
Faculty of Electronics

The Department of Design of Electronic Digital Equipment (DEDEC)
The Laboratory of Digital Technologies
room 339, building 12, 16 Politekhnicheskaya st.
Kyiv, 03056, Ukraine
Phone:+380-44-454-93-63, +380-44-454-95-38
Email: o.lysenko@kpi.ua

http://www.digitallab.kiev.ua